module sll64_partial (indata,val,outdata);
parameter width=6; //[6:0]
input [63:0] indata;
input [width:0] val;
output [63:0] outdata;
assign outdata=indata<<val;
endmodule
Flow Status Successful - Fri Feb 22 01:17:37 2013
Quartus II 64-Bit Version 12.1 Build 177 11/07/2012 SJ Web Edition
Revision Name caddr
Top-level Entity Name caddr
Family Cyclone IV GX
Device EP4CGX150DF31I7AD
Timing Models Final
Total logic elements 2,929 / 149,760 ( 2 % )
Total combinational functions 2,860 / 149,760 ( 2 % )
Dedicated logic registers 471 / 149,760 ( < 1 % )
Total registers 471
Total pins 27 / 508 ( 5 % )
Total virtual pins 0
Total memory bits 0 / 6,635,520 ( 0 % )
Embedded Multiplier 9-bit elements 0 / 720 ( 0 % )
Total GXB Receiver Channel PCS 0 / 8 ( 0 % )
Total GXB Receiver Channel PMA 0 / 8 ( 0 % )
Total GXB Transmitter Channel PCS 0 / 8 ( 0 % )
Total GXB Transmitter Channel PMA 0 / 8 ( 0 % )
Total PLLs 0 / 8 ( 0 % )2929LEですと？ちょっと少なすぎるみたいだけどもここからRAMを盛っていく。
Flow Status Flow Failed - Wed Feb 20 18:15:59 2013Quartus II 64-Bit Version 12.1 Build 177 11/07/2012 SJ Web EditionRevision Name caddrTop-level Entity Name caddrFamily Cyclone IV GXDevice EP4CGX150DF31I7ADTiming Models FinalTotal logic elements 169,055 / 149,760 ( 113 % )Total combinational functions 109,428 / 149,760 ( 73 % )Dedicated logic registers 136,714 / 149,760 ( 91 % )Total registers 136714Total pins 27 / 508 ( 5 % )Total virtual pins 0Total memory bits 787,040 / 6,635,520 ( 12 % )Embedded Multiplier 9-bit elements 0 / 720 ( 0 % )Total GXB Receiver Channel PCS 0 / 8 ( 0 % )Total GXB Receiver Channel PMA 0 / 8 ( 0 % )Total GXB Transmitter Channel PCS 0 / 8 ( 0 % )Total GXB Transmitter Channel PMA 0 / 8 ( 0 % )Total PLLs 0 / 8 ( 0 % )
module apll ( inclk0, c0); input inclk0; output c0; endmoduleこれをつないでやれば良い。トップモジュールで定義したクロック入力をclk_50、PLLの出力をclkで分配すると
module bcdmod3(BCD,BCDout);
input [3:0] BCD;
output [3:0] BCDout;
function [3:0] mod3;
input [3:0] bcdin;
begin
case (bcdin)
1: mod3=1;
2: mod3=2;
4: mod3=1;
5: mod3=2;
7: mod3=1;
8: mod3=2;
default: mod3=0;
endcase
end
endfunction
assign BCDout=mod3(BCD);
endmodule
module chkfizz(BCD3,BCD2,BCD1,BCD0, fizz);
input [3:0] BCD3;
input [3:0] BCD2;
input [3:0] BCD1;
input [3:0] BCD0;
output fizz;
wire [3:0] sBCD3;
wire [3:0] sBCD2;
wire [3:0] sBCD1;
wire [3:0] sBCD0;
wire [3:0] tBCD;
wire [3:0] aBCD;
bcdmod3 bcdmod3_3(BCD3,sBCD3);
bcdmod3 bcdmod3_2(BCD2,sBCD2);
bcdmod3 bcdmod3_1(BCD1,sBCD1);
bcdmod3 bcdmod3_0(BCD0,sBCD0);
assign tBCD=sBCD3+sBCD2+sBCD1+sBCD0;
bcdmod3 bcdmod3_a(tBCD,aBCD);
assign fizz=(aBCD==4'd0);
endmodule
// terasIC DE0 topmodule skeleton
// onboard I/O 3-button,10-sw,10-LED,4-7SEG
//
module Skeleton(clk,btn,sw,led,hled0,hled1,hled2,hled3,lcd_bl);
input clk;
input [2:0] btn;
input [9:0] sw;
output [9:0] led;
output [7:0] hled0;
output [7:0] hled1;
output [7:0] hled2;
output [7:0] hled3;
output lcd_bl;
assign led=(btn[2]==1'b1) ? sw: ~sw; // button2 press, then invert all LED
assign hled0[7:0]=(btn[1:0]==2'b11) ? ~sw[7:0]: 8'b11111111; // 7segment digit xxx0
assign hled1[7:0]=(btn[1:0]==2'b10) ? ~sw[7:0]: 8'b11111111; // 7segment digit xx0x press button 0
assign hled2[7:0]=(btn[1:0]==2'b01) ? ~sw[7:0]: 8'b11111111; // 7segment digit x0xx press button 1
assign hled3[7:0]=(btn[1:0]==2'b00) ? ~sw[7:0]: 8'b11111111; // 7segment digit 0xxx press button 1,0
assign lcd_bl=sw[9]; // optiona LCD backlight
endmodule
module Lesson1( sw, led );
input [9:0] sw ;
output [9:0] led ;
assign led=sw;
endmodule
/*
module Lesson1(
sw0,sw1,sw2,sw3,sw4,sw5,sw6,sw7,sw8,sw9,
led0,led1,led2,led3,led4,led5,led6,led7,led8,led9);
input sw0,sw1,sw2,sw3,sw4,sw5,sw6,sw7,sw8,sw9;
output led0,led1,led2,led3,led4,led5,led6,led7,led8,led9;
assign led0=sw0;
assign led1=sw1;
assign led2=sw2;
assign led3=sw3;
assign led4=sw4;
assign led5=sw5;
assign led6=sw6;
assign led7=sw7;
assign led8=sw8;
assign led9=sw9;
endmodule
*/
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